DK-DEV-5SGXEA7N【PDF 34/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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2-12

Clocking Modes for Each Memory Mode

SV51003

2013.05.06

Clocking Modes for Each Memory Mode

Table 2-10: Memory Blocks Clocking Modes Supported for Each Memory Mode

Memory Mode

Clocking Mode

Single-Port

Simple Dual-

True Dual-

ROM

FIFO

Port

Port

Single clock mode

Read/write clock mode

Input/output clock mode

Independent clock mode

Yes

—

Yes

—

Yes

Yes

Yes

—

Yes

—

Yes

Yes

Yes

—

Yes

Yes

Yes

Yes

—

—

Note: The clock enable signals are not supported for write address, byte enable, and data input registers

on MLAB blocks.

Single Clock Mode

In the single clock mode, a single clock, together with a clock enable, controls all registers of the memory

block.

Read/Write Clock Mode

In the read/write clock mode, a separate clock is available for each read and write port. A read clock controls

the data-output, read-address, and read-enable registers. A write clock controls the data-input, write-address,

write-enable, and byte enable registers.

Input/Output Clock Mode

In input/output clock mode, a separate clock is available for each input and output port. An input clock

controls all registers related to the data input to the memory block including data, address, byte enables,

read enables, and write enables. An output clock controls the data output registers.

Independent Clock Mode

In the independent clock mode, a separate clock is available for each port (A and B). Clock A controls all

registers on the port A side; clock B controls all registers on the port B side.

Note: You can create independent clock enable for different input and output registers to control the shut

down of a particular register for power saving purposes. From the parameter editor, click More

Options (beside the clock enable option) to set the available independent clock enable that you prefer.

Asynchronous Clears in Clocking Modes

In all clocking modes, asynchronous clears are available only for output latches and output registers. For

the independent clock mode, this is applicable on both ports.

Altera Corporation

Embedded Memory Blocks in Stratix V Devices

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